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cadenceIC610安装错误总结(四)(图文教程)

时间:2024-10-13 05:43:30

1、在IC610过程中,若出现下列的提示,则说明license本身就是不对的。

cadenceIC610安装错误总结(四)(图文教程)

2、所以,要设置一个正确的license才可以的。[redhat3@haidee license]$ lmli[redhat3@haidee license]$ icfb&[1] 8624[redhat3@haidee license]$ 15:42:15 (lmgrd) -----------------------------------------------15:42:15 (lmgrd) Please Note:15:42:15 (lmgrd)15:42:15 (lmgrd) This log is intended for debug purposes only.15:42:15 (lmgrd) In order to capture accurate license15:42:15 (lmgrd) usage data into an organized repository,15:42:15 (lmgrd) please enable report logging. Use Macrovision's15:42:15 (lmgrd) software license administration solution,15:42:15 (lmgrd) FLEXnet Manager, to readily gain visibility15:42:15 (lmgrd) into license usage data and to create15:42:15 (lmgrd) insightful reports on critical information like15:42:15 (lmgrd) license availability and usage. FLEXnet Manager15:42:15 (lmgrd) can be fully automated to run these reports on15:42:15 (lmgrd) schedule and can be used to track license15:42:15 (lmgrd) servers and usage across a heterogeneous15:42:15 (lmgrd) network of servers including Windows NT, Linux15:42:15 (lmgrd) and UNIX. Contact Macrovision at15:42:15 (lmgrd) www.macrovision.com for more details on how to15:42:15 (lmgrd) obtain an evaluation copy of FLEXnet Manager15:42:15 (lmgrd) for your enterprise.15:42:15 (lmgrd)15:42:15 (lmgrd) -----------------------------------------------15:42:15 (lmgrd)15:42:15 (lmgrd)15:42:15 (lmgrd) The TCP port number in the license, 5280, is already in use.15:42:15 (lmgrd) Possible causes:15:42:15 (lmgrd) 1) The license server manager (lmgrd) is already running for this license.15:42:15 (lmgrd) 2) The OS has not "cleared" this port since lmgrd died.15:42:15 (lmgrd) 3) Another process is using this port number (unlikely).15:42:15 (lmgrd) Solutions:15:42:15 (lmgrd) 1) Make sure lmgrd and all vendor daemons for this15:42:15 (lmgrd) license are not running.15:42:15 (lmgrd) 2) You may have to wait for the OS to clear this port.15:42:15 (lmgrd) Retrying for about 5 more minutes15:42:33 (lmgrd) Still trying...15:42:51 (lmgrd) Still trying...15:43:09 (lmgrd) Still trying...15:43:27 (lmgrd) Still trying...15:43:45 (lmgrd) Still trying...15:44:03 (lmgrd) Still trying...15:44:21 (lmgrd) Still trying...15:44:39 (lmgrd) Still trying...15:44:57 (lmgrd) Still trying...15:45:15 (lmgrd) Still trying...15:45:33 (lmgrd) Still trying...15:45:48 (lmgrd) Failed to open the TCP port number in the license.

cadenceIC610安装错误总结(四)(图文教程)

3、若对于正确的license,还是有问题的话,这时候就需要重新启动

cadenceIC610安装错误总结(四)(图文教程)

4、重新启动后,一定要执行lmli指令,下面是执行lmli后的界面。[redhat3@haidee redhat3]$ lmli[redh锾攒揉敫at3@haidee redhat3]$ 17:32:50 (lmgrd) -----------------------------------------------17:32:50 (lmgrd) Please Note:17:32:50 (lmgrd)17:32:50 (lmgrd) This log is intended for debug purposes only.17:32:50 (lmgrd) In order to capture accurate license17:32:50 (lmgrd) usage data into an organized repository,17:32:50 (lmgrd) please enable report logging. Use Macrovision's17:32:50 (lmgrd) software license administration solution,17:32:50 (lmgrd) FLEXnet Manager, to readily gain visibility17:32:50 (lmgrd) into license usage data and to create17:32:50 (lmgrd) insightful reports on critical information like17:32:50 (lmgrd) license availability and usage. FLEXnet Manager17:32:50 (lmgrd) can be fully automated to run these reports on17:32:50 (lmgrd) schedule and can be used to track license17:32:50 (lmgrd) servers and usage across a heterogeneous17:32:50 (lmgrd) network of servers including Windows NT, Linux17:32:50 (lmgrd) and UNIX. Contact Macrovision at17:32:50 (lmgrd) www.macrovision.com for more details on how to17:32:50 (lmgrd) obtain an evaluation copy of FLEXnet Manager17:32:50 (lmgrd) for your enterprise.17:32:50 (lmgrd)17:32:50 (lmgrd) -----------------------------------------------17:32:50 (lmgrd)17:32:50 (lmgrd)17:32:50 (lmgrd) FLEXnet Licensing (v10.8.0.7 build 26147) started on haidee (linux) (7/16/2011)17:32:50 (lmgrd) Copyright (c) 1988-2006 Macrovision Europe Ltd. and/or Macrovision Corporation. All Rights Reserved.17:32:50 (lmgrd) US Patents 5,390,297 and 5,671,412.17:32:50 (lmgrd) World Wide Web: http://www.macrovision.com17:32:50 (lmgrd) License file(s): /home/eda/ic610/share/license/license.dat17:32:50 (lmgrd) lmgrd tcp-port 528017:32:50 (lmgrd) Starting vendor daemons ...17:32:50 (lmgrd) Started cdslmd (internet tcp_port 32777 pid 2024)17:32:50 (cdslmd) FLEXnet Licensing version v10.8.0.7 build 2614717:32:50 (cdslmd) Invalid license key (inconsistent authentication code)17:32:50 (cdslmd) ==>FEATURE Cadence_3D_Design_Viewer cdslmd 16.0 31-dec-2025 uncounted \ 01357D06E4AD VENDOR_STRING=Team_EFA_2006 HOSTID=ANY ck=78 \ SIGN2="0D0D EA79 E0C1 4F48 4DCF 770A E1AE F9EF 70FB FF11 B46D \ CB35 F1D2 9A45 F4A3 05E1 EB0A CEF4 8396 87BA 7B4A BA27 CED9 \ F214 BED4 2DC6 BF6A F385 8BDA C611"17:32:50 (cdslmd) Invalid license key (inconsistent authentication code)17:32:50 (cdslmd) ==>FEATURE Capture cdslmd 16.0 31-dec-2025 uncounted FC5BE9761A8C \ VENDOR_STRING=Team_EFA_2006 HOSTID=ANY ck=115 SIGN2="172D DEBE \ A0EB 398F CC4A 6F83 94C4 9562 ED81 D592 F833 18A4 F5A7 009E \ EBE4 0F57 1D31 3017 21F4 CE68 9C92 4062 39AF 69FA 9B04 DEA3 \ F3BB 5CF1 2709 1BDA"17:32:50 (cdslmd) Server started on haidee for: LayoutPlus17:32:50 (cdslmd) Allegro_Librarian Allegro_Viewer_Plus PspiceAD17:32:50 (cdslmd) PspiceAA Allegro_studio ConceptHDL17:32:50 (cdslmd) PCB_librarian_expert SiP_Digital_Architect_GXL SiP_Digital_Architect_L17:32:50 (cdslmd) SiP_Digital_Architect_XL SiP_Digital_Layout_GXL SiP_Digital_SI_XL17:32:50 (cdslmd) SiP_RF_Architect_L SiP_RF_Architect_XL SiP_RF_Layout_GXL17:32:50 (cdslmd) Allegro_Design_Editor_620 Allegro_PCB_SI_230 Allegro_PCB_SI_63017:32:50 (cdslmd) SPECCTRAQuest_EE PCB_designer CHDL_DesignAccess17:32:50 (cdslmd) PE_Librarian Checkplus_Expert Concept_HDL_rules_checker17:32:50 (cdslmd) Concept_HDL_studio PCB_design_studio adv_package_designer_expert17:32:50 (cdslmd) PCB_studio_variants PCB_design_expert adv_package_engineer_expert17:32:50 (cdslmd) SPECCTRAQuest_SI_expert Concept_HDL_expert Allegro_design_expert17:32:50 (cdslmd) advanced_package_designer Allegro_designer_suite OrCAD_PCB_Router17:32:50 (cdslmd) OrCAD_PCB_Designer_PSpice OrCAD_PCB_Designer UNISON_SPECCTRA_6U17:32:50 (cdslmd) SPECCTRA_Unison_Ultra SPECCTRA_Unison_PCB Unison_SPECCTRA_4U17:32:50 (cdslmd) Allegro_PCB_Design_620 Allegro_Package_SI_620_Suite Allegro_PCB_SI_62017:32:50 (cdslmd) Allegro_Pkg_Designer_620_Suite Allegro_PCB_Router_230 Allegro_PCB_Design_23017:32:50 (cdslmd) Allegro_PCB_SI_630_Suite Allegro_PCB_Router_210 Allegro_PCB_Router_61017:32:50 (cdslmd) SPECCTRA_VT SPECCTRA_QE SPECCTRA_performance17:32:50 (cdslmd) SPECCTRA_PCB SPECCTRA_HP SPECCTRA_expert_system17:32:50 (cdslmd) SPECCTRA_expert SPECCTRA_DFM SPECCTRA_autoroute17:32:50 (cdslmd) SPECCTRA_APD SPECCTRA_ADV SPECCTRA_6U17:32:50 (cdslmd) SPECCTRA_256U Allegro_performance Allegro_PCB_RF17:32:50 (cdslmd) Allegro_PCB_Partitioning Advanced_Pkg_Engineer_3D PowerIntegrity17:32:50 (cdslmd) SPECCTRAQuest 111 1214117:32:50 (cdslmd) 14000 14010 1402017:32:50 (cdslmd) 14040 14060 20617:32:50 (cdslmd) 207 21060 2140017:32:50 (cdslmd) 276 283 30017:32:50 (cdslmd) 3000 3001 301117:32:50 (cdslmd) 302 305 31117:32:50 (cdslmd) 3111 32100 3210117:32:50 (cdslmd) 32120 32125 3213017:32:50 (cdslmd) 32140 32150 3250017:32:50 (cdslmd) 32501 32505 3251017:32:50 (cdslmd) 32520 32521 3253017:32:50 (cdslmd) 32760 33015 3301617:32:50 (cdslmd) 33301 33500 3358017:32:50 (cdslmd) 34500 34510 3451117:32:50 (cdslmd) 34530 34570 3458017:32:50 (cdslmd) 365 370 3710017:32:50 (cdslmd) 374 38500 3852017:32:50 (cdslmd) 4000 501 510017:32:50 (cdslmd) 550 570 68117:32:50 (cdslmd) 70000 70110 7012017:32:50 (cdslmd) 70130 70510 7052017:32:50 (cdslmd) 71110 71120 7113017:32:50 (cdslmd) 71510 71520 7351017:32:50 (cdslmd) 73520 900 9000117:32:50 (cdslmd) 940 945 9510017:32:50 (cdslmd) 95115 95120 95217:32:50 (cdslmd) 95200 95210 9522017:32:50 (cdslmd) 95255 95300 9531017:32:50 (cdslmd) 95320 95400 97217:32:50 (cdslmd) 974 plotVersa LEAPFROG-CV17:32:50 (cdslmd) _21900 Datapath_Preview_Option Virtuoso_Turbo17:32:50 (cdslmd) Virtuoso_XL Encounter_C Virtuoso_Digital_Implement17:32:50 (cdslmd) Virtuoso_XL_Basic Virtuoso_Schem_Option Virtuoso_Turbo_Basic17:32:50 (cdslmd) OASIS_Simulation_Interface OASIS_RFDE Artist_Optimizer17:32:50 (cdslmd) Artist_Statistics Corners_Analysis Affirma_3rdParty_Sim_Interface17:32:50 (cdslmd) Affirma_RF_IC_package_modeler SpectreRF Substrate_Coupling_Analysis17:32:50 (cdslmd) Affirma_RF_SPW_model_link Virtuoso_Core_Optimizer Virtuoso_Core_Characterizer17:32:50 (cdslmd) ULTRASIM RELXPERT UET17:32:50 (cdslmd) Affirma_AMS_distrib_processing ADE_VoltageStorm_Option ADE_ElectronStorm_Option17:32:50 (cdslmd) LAS_Cell_Optimization Virtuoso_Spectre Virtuoso_Spectre_RF17:32:50 (cdslmd) virtuoso_chip_editor Virtuoso_Layout_Migrate ConcICe_Option17:32:50 (cdslmd) AMS_environment DRAC2CORE DRAC3CORE17:32:50 (cdslmd) DRAC3DRC DRACDIST DRACERC17:32:50 (cdslmd) Distributed_Dracula_Option DRAC3LVS DRACLPE17:32:50 (cdslmd) DRACPRE DRACLVS Assura_RCX-PL17:32:50 (cdslmd) Assura_RCX-FS Assura_RCX-MP Assura_RCX-HF17:32:50 (cdslmd) Assura_DRC Assura_LVS Assura_MP17:32:50 (cdslmd) Assura_OPC Assura_RCX Assura_SI-TL17:32:50 (cdslmd) Assura_SI Assura_SiMC Assura_SiVL17:32:50 (cdslmd) Assura_UI Assura_DV_design_rule_checker Assura_DV_parasitic_extractor17:32:50 (cdslmd) Assura_DV_LVS_checker Physical_Verification_Sys_L Physical_Verification_Sys_XL17:32:50 (cdslmd) skillDev Affirma_sim_analysis_env Virtuoso_Multi_mode_Simulation17:32:50 (cdslmd) Virtuoso_Schematic_Editor_L Virtuoso_Schematic_Editor_XL Virtuoso_Schematic_Editor_GXL17:32:50 (cdslmd) Composer_EDIF300_Connectivity Analog_Design_Environment_L Analog_Design_Environment_XL17:32:50 (cdslmd) Analog_Design_Environment_GXL Virtuoso_Visual_Analysis_XL Composer_EDIF300_Schematic17:32:50 (cdslmd) Virtuoso_Layout_Suite_L Virtuoso_Layout_Suite_XL Virtuoso_Layout_Suite_GXL17:32:50 (cdslmd) Virtuoso_Constraint_API Spectre_BTAHVMOS_Models Spectre_BTASOI_Models17:32:50 (cdslmd) tw01 tw0217:32:50 (cdslmd)17:32:50 (cdslmd) All FEATURE lines for cdslmd behave like INCREMENT lines17:32:50 (cdslmd)17:32:50 (lmgrd) cdslmd using TCP-port 32777

5、上面的提示说明license是正确的,然后再启动ic610[redhat3@haidee redhat3]$ icfb&[1] 2043[redhat3@haidee redhat3]$ 17:34:34 (cdslmd) OUT: "Virtuoso_Schematic_Editor_L" redhat3@haidee[redhat3@haidee redhat3]$

cadenceIC610安装错误总结(四)(图文教程)
cadenceIC610安装错误总结(四)(图文教程)

6、成功打开后,就可以建立cell了,以图为例。

cadenceIC610安装错误总结(四)(图文教程)
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